Low-k dielectric materials are known to improve chip resistance-capacitance (RC) delay, minimize cross talk noise, and reduce power dissipation. These low-k dielectric materials are thus indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high performance logic circuits. However, with the wide application of low-k and ultralow-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming one of the most critical challenges for technology qualification. For example, low-k time dependent dielectric breakdown (TDDB) is commonly considered an important reliability issue because low-k materials generally have lower intrinsic breakdown strengths than traditional SiO2 dielectrics. This problem is further exacerbated by the aggressive shrinking of interconnect spacing resulting from continuous technology scaling.
In order for the process community to improve low-k dielectric TDDB performance, it is necessary to identify early fails and failure modes. To obtain meaningful TDDB data which can be used to identify yield/defect problems and the weak point of the process, test structures have to have large critical area. However, it is very difficult to pin point the exact location and the cause of failure with current methods of TDDB stress and failure analysis.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.